1. Field of the Invention
This invention relates to capacitors for DRAMs and more particularly to lower electrodes of crown capacitors with fins or to lower electrodes of stack capacitors.
2. Description of Related Art
U.S. Pat. No. 5,208,180 of Gonzalez shows a xe2x80x9cMethod of Forming a Capacitorxe2x80x9d using a oxide etching process.
U.S. Pat. No. 5,532,182 of Woo for a xe2x80x9cMethod for Fabricating Stacked Capacitor of a DRAM Cellxe2x80x9d shows a fin type capacitor using doped and undoped amorphous Si layers.
U.S. Pat. No. 5,573,967 of Tseng describes a xe2x80x9cMethod for Making Dynamic Random Access Memory with Fin-type Stacked Capacitorxe2x80x9d.
U.S. Pat. No. 5,631,184 of Ikemasu et al. describes a xe2x80x9cMethod of Producing a Semiconductor Device Having a Fin-type Capacitor.xe2x80x9d
U.S. Pat. No. 5,637,523 of Fazan describes a xe2x80x9cMethod for Forming a Capacitor and a Capacitor Structurexe2x80x9d shows a in type capacitor formed by etching doped and undoped polysilicon layers.
U.S. Pat. No. 5,656,536 of Wu describes a xe2x80x9cMethod of Manufacturing a Crown Shaped Capacitor with Horizontal Fins for High Density DRAMS.xe2x80x9d
A fin structure can be made by alternately depositing silicon nitride (Si3N4) and silicon dioxide (SiO2) and dipping back and then filling with a polysilicon layer which is a complicated process.
A crown or stack capacitor with a fin structure is made with a different silicon dioxide etching rate in a vapor of hydrogen fluoride HF acid environment.
This invention teaches a method of forming a fin structure using a combination of both doped and undoped silicon dioxide layers with a bulk or a thin film second conductive layer formed into a capacitor core. The core can be composed of a monolithic body of conductive material.
In accordance with this invention, a process of forming an electrode comprises the steps of formation of a capacitor core formed on a semiconductor device which contains doped regions in the surface thereof blanketed with a dielectric layer which contains a conductive plug extending therethrough which contacts one of the doped regions in the semiconductor substrate.
First, form a sublayer comprising a first conductive layer in contact with a plug which contacts one of the doped regions in the semiconductor substrate. Form a mold from a stack of silicon dioxide layers which are alternatingly an undoped layer covered with a doped layer on the sublayer comprising the first conductive layer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold. Deposit a layer of polysilicon into the cavity forming a capacitor core with counterpart ribs cantilevered (projecting) with a complementary pattern to the mold and the capacitor core having a top surface. Polish the capacitor core to remove the top surface of the core, and remove the mold.
Preferably, the mold is etched with a combination of hydrogen fluoride vapor and water vapor.
In one embodiment, the core is formed of a solid deposit of a second conductive layer which fills the cavity. The dopant comprises boron and phosphorus and the mold is etched with a combination of hydrogen fluoride vapor and water vapor.
Preferably, the dopant comprises boron and phosphorus, and the mold is etched with a combination of hydrogen fluoride vapor and water vapor.
The core is planarized by a CMP process which removes a top undoped layer of the mold whereby the core has a flat upper surface with a rib located on top of the core, and etch back the sublayer comprising a first thin conductive layer to separate the core from adjacent cores.
Alternatively one can deposit a thin layer of a second conductive layer such as polysilicon into the cavity. Then, form a thin capacitor core with an array of counterpart cantilevered (projecting) ribs with a pattern which is complementary to the pattern of the mold. The capacitor core has a top surface.
In the case of the thin layer of the second conductive layer, next deposit a photoresist layer into the inner cavity filling the inner cavity. Then polish the capacitor core to remove the top surface of the core, and remove the photoresist and remove the mold.
Then etch back the sublayer comprising a first thin conductive layer to separate the core from adjacent cores.
Preferably, the core is a monolithic core.
In accordance with another aspect of this invention, a monolithic capacitor core is formed on a semiconductor device. A sublayer comprising a first conductive layer is formed in contact with a plug which contacts a doped first conductive region in the semiconductor substrate. A second conductive layer is formed into a monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of the monolithic core. The monolithic capacitor core has a cantilevered top surface projecting from the exterior sidewall of the monolithic core.
Preferably the second conductive layer is formed into a hollow monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of the monolithic core and a base covering the first conductive layer. It that case it is preferred that the second conductive layer formed into a monolithic core is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride, and said second conductive layer has a thickness from about 500 xc3x85 to about 1,000 xc3x85.
Alternatively, the second conductive layer is formed as a solid monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of the monolithic core and the core covering the first conductive layer.